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• CS5506 datasheet
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CS5505/6/7/8
Very Low Power, 16-bit & 20-bit A/D Converters
Features
l Very Low Power Consumption
- Single supply +5 V operation: 1.7 mW
- Dual supply ±5 V operation: 3.2 mW
l Offers superior performance to VFCs and multi-slope integrating ADCs
l Differential Inputs
- Single Channel (CS5507/8) and Four-Channel
(CS5505/6) pseudo-differential versions
l Either 5 V or 3.3 V Digital Interface
l Linearity Error:
- ±0.0015% FS (16-bit CS5505/7)
- ±0.0007% FS (20-bit CS5506/8)
l Output update rates up to 100 Sps
l Flexible Serial Port
l Pin-Selectable Unipolar/Bipolar Ranges
Description
The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes.
The CS5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample upon command up to 100 Sps.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
The CS5505/6/7/8 include on-chip self-calibration cir- cuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors.
The CS5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers or syn- chronous serial ports of industry-standard microcontrollers.
ORDERING INFORMATION
See page 30.
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Copyright �Cirrus Logic, Inc. 2009 (All Rights Reserved)
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ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ï‚?10%; VA- = -5V ï‚?10%; VD+ =
3.3V �5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1k�with a 10nF
to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
Parameter*
CS5505/7-A
Min Typ Max
Specified Temperature Range
-40 to +85
Accuracy
Linearity Error
- 0.0015 0.003
Differential Nonlinearity
- ï‚?.25 ï‚?.5
Full Scale Error (Note 3)
- ï‚?.25 ï‚?
Full Scale Drift (Note 4)
- ï‚?.5 -
Unipolar Offset (Note 3)
- ï‚?.5 ï‚?
Unipolar Offset Drift (Note 4)
- ï‚?.5 -
Bipolar Offset (Note 3)
- ï‚?.25 ï‚?
Bipolar Offset Drift (Note 4)
- ï‚?.25 -
Noise (Referred to Output)
- 0.16 -
LSB- rms16
Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the
text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25ï‚°C.
Recalibration at any temperature will remove these errors.
Unipolar Mode
LSB’s % FS ppm FS
Bipolar Mode
LSB’s % FS ppm FS
0.26 0.0004 4
0.13 0.0002 2
0.50 0.0008 8
0.26 0.0004 4
1.00 0.0015 15
0.50 0.0008 8
2.00 0.0030 30
1.00 0.0015 15
4.00 0.0061 61
2.00 0.0030 30
VREF = 2.5V
CS5505/7; 16-Bit Unit Conversion Factors
* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ï‚?10%; VA- = -5V ï‚?10%; VD+ =
3.3V �5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1k�with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
Parameter*
CS5506/8-B
Min Typ Max
Specified Temperature Range
-40 to +85
Accuracy
Linearity Error
- 0.0007 0.0015
Differential Nonlinearity
(No Missing Codes)
Full Scale Error (Note 3)
- ï‚? ï‚?2
Full Scale Drift (Note 4)
- ï‚? -
Unipolar Offset (Note 3)
- ï‚? ï‚?2
Unipolar Offset Drift (Note 4)
- ï‚? -
Bipolar Offset (Note 3)
- ï‚? ï‚?6
Bipolar Offset Drift (Note 4)
- ï‚? -
Noise (Referred to Output)
- 2.6 -
LSB- rms20
Unipolar Mode
LSB’s % FS ppm FS
Bipolar Mode
LSB’s % FS ppm FS
0.25 0.0000238 0.24
0.13 0.0000119 0.12
0.50 0.0000477 0.47
0.26 0.0000238 0.24
1.00 0.0000954 0.95
0.50 0.0000477 0.47
2.00 0.0001907 1.91
1.00 0.0000954 0.95
4.00 0.0003814 3.81
2.00 0.0001907 1.91
VREF = 2.5V
CS5506/8; 20-Bit Unit Conversion Factors
DYNAMIC CHARACTERISTICS
Parameter
Symbol
Modulator Sampling Frequency
fclk/2
Output Update Rate (CONV = 1)
fclk/1622
Filter Corner Frequency
fclk/1928
Settling Time to 1� LSB (FS Step)
1/fout
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ï‚?10%; VA- = -5V ï‚?10%; VD+ =
3.3V �5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1k�with a
10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2)
Parameter*
CS5505/7
CS5506/8
Min Typ Max
Specified Temperature Range
-40 to +85
Analog Input
Analog Input Range: Unipolar
(VAIN+)-(VAIN-) Bipolar (Note 5)
0 to +2.5
Common Mode Rejection: dc
50, 60 Hz (Note 6)
- 105 -
120 - -
Off Channel Isolation
- 120 -
Input Capacitance
- 15 -
DC Bias Current (Note 1)
Voltage Reference (Output)
VREFOUT Voltage
- (VA+)-2.5 -
VREFOUT Voltage Tolerance
- - 4.0
VREFOUT Voltage Temperature Coefficient
- 60 -
ppm/ï‚°C
VREFOUT Line Regulation
- 1.5 -
mV/Volt
VREFOUT Output Voltage Noise
0.1 to 10 Hz
VREFOUT: Source Current
Sink Current
Power Supplies
DC Power Supply Currents: ITotal IAnalog IDigital
- 340 450
- 300 -
Power Dissipation: (Note 7) SLEEP inactive SLEEP active
- 3.2 4.5
Power Supply Rejection: Positive Supplies
Negative Supplies
- 80 -
Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. XIN = 32.768 kHz. Guaranteed by design and / or characterization.
7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin.
SLEEP active = M/SLP pin at (VD+)/2 input level.
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ï‚?10%; VA-= -5V ï‚?10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
Symbol
High-Level Input Voltage: XIN M/SLP
All Pins Except XIN and M/SLP
VIH VIH VIH
Low-Level Input Voltage: XIN M/SLP
All Pins Except XIN and M/SLP
VIL VIL VIL
M/SLP SLEEP Active Threshold (Note 8)
0.45VD+
0.5VD+
0.55VD+
High-Level Output Voltage (Note 9)
(VD+)-1.0
Low Level Output Voltage Iout = 1.6 mA
Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance
Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. Iout = -100 A. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 A).
3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ï‚?10%; VD+ = 3.3V ï‚?5%; VA-= -5V ï‚?10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
Symbol
High-Level Input Voltage: XIN M/SLP
All Pins Except XIN and M/SLP
VIH VIH VIH
0.7VD+
Low-Level Input Voltage: XIN M/SLP
All Pins Except XIN and M/SLP
VIL VIL VIL
0.3VD+
0.16VD+
M/SLP SLEEP Active Threshold (Note 8)
0.43VD+
0.45VD+
0.47VD+
High-Level Output Voltage Iout = -400 A
(VD+)-0.3
Low Level Output Voltage Iout = 400 A
Input Leakage Current
3-State Leakage Current
Digital Output Pin Capacitance
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ï‚?10%; VA- = -5V ï‚?10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol
Master Clock Frequency: Internal Oscillator:
External Clock:
32.768
Master Clock Duty Cycle
Rise Times: Any Digital Input (Note 10) Any Digital Output
Fall Times: Any Digital Input (Note 10) Any Digital Output
Start-Up
Power-On Reset Period (Note 11)
Oscillator Start-up Time XTAL=32.768 kHz (Note 12)
Wake-up Period (Note 13)
1800/fclk
Calibration
CONV Pulse Width (CAL = 1) (Note 14)
CONV and CAL High to Start of Calibration
2/fclk+200
Start of Calibration to End of Calibration
3246/fclk
Conversion
Set Up Time